Complete ATSC (VSB)/NTSC channel
decoding solution with just two ICs
This chipset combines Philips' long experience in analog TV with our
innovative approach to DTV, creating an outstanding system solution
showcasing Philips' mixed signal technology expertise and offering very
high levels of integration, performance and flexibility. Designed for
analog and digital TV systems in North America and other ATSC
countries, the chipset enables manufacturers to design systems offering
end-users significantly improved reception at an attractive price.
The two key chips featured are the TDA8980 TV input processor and
the TDA8961 8-VSB demodulator/decoder for the ATSC DTV
standard. Designed specifically to reduce the chip count of first
generation front-ends, the TDA8980 eliminates many components by
integrating NTSC decoding, an IF circuit, picture and sound
demodulation and VSB downconversion, all into a single device.
This chipset gives true design flexibility, with the TDA8980 offering
both analog and digital capability, with comprehensive analog source
selection and also providing format conversion. This ensures glueless
support for the many legacy inputs a digital hybrid receiver is likely to
require.
Benefiting from real-world experience of VSB reception, Philips' second
generation VSB demodulator handles the many problems caused by
man-made and naturally occurring echoes. Intelligent techniques in the
decoder allow it to cope with the delays and reflections caused by indoor
environments full of objects and moving people. Its maximum equalizer
length of 80
s in conjunction with external software allows the receiver
to cope with very long static echoes. Patented NTSC co-channel
interference technology prevents strong NTSC signals from interfering
with their less powerful DTV counterparts on the same channel, without
the noise penalty associated with regular comb filter schemes.
As the roll out of digital TV accelerates, DTV receiver
manufacturers are looking for improved performance, flexibility
and cost reductions to meet the demands of the consumer
market. Philips' latest reference design meets these stringent
requirements, using two new ICs, the second generation
TDA8961 VSB demodulator and the TDA8980 integrated
ATSC/NTSC TV input processor
Applications
Digital ATSC/NTSC-compliant TV receivers and
Set Top Converters
DTV-equipped PC/multimedia applications
Tightly integrated, flexible DTV front-end
Second generation ATSC/NTSC channel decoding
chipset
Greatly reduced chip count due to single-chip
ATSC/NTSC TV input processor providing
NTSC TV decoding and VSB IF downconversion
Analog source selection and format conversion
High performance reception
Urban reception improvement
Unique co-channel filter to reduce interference
from strong NTSC signals
Ability to handle very long static echoes (up to 80
s) in
conjunction with external software
ATSC/NTSC digital TV
front-end chipset
Second generation chipset
TDA8980HL ATSC/NTSC TV
INPUT PROCESSOR
Key features
NTSC-M colour decoder tuned with a
12 MHz reference crystal
(or external clock signal)
VSB IF circuit for pre-processing
DTV signals
Alignment-free PLL demodulator Vision
IF circuit without external components
Sound IF amplifier with separate input
for single reference QSS mode and
separate AGC circuit
Alignment-free FM sound demodulator
generates the input signal for a BTSC
stereo decoder
Video source selection with 2 external
CVBS or Y/C inputs and an
independently switchable output
Two 10-bit video ADCs for converting
selected YUV signals (video mode)
or downconverted I&Q signals
(VSB mode)
Two 16-bit audio A/D converters and
I
2
S formatter
Up to four stereo analog inputs and
one I
2
S input
ITU656 or VSB formatter
Direct input to video ADCs
Integrating many components into a single
chip, the TDA8980HL is designed for both
TV and multimedia applications. Containing
an NTSC-M colour decoder, an IF circuit
and ADCs for audio and video, it can also
generate a `mixed down' I signal for
demodulation of a digital broadcast VSB
input. An I
2
C-bus controlled internal switch
enables the device to switch between analog
NTSC and digital 8-VSB IF signals.
When decoding NTSC, the chip digitizes the audio signals into an
I
2
S stream using on-chip audio stereo 16-bit ADCs, and the video
information into an ITU656 stream via the on-chip video ADCs.
An incoming 6 MHz wide 8-VSB IF signal is downconverted to a low
IF, centred at 4 MHz, which is digitized using an on-chip 10-bit ADC
and gluelessly interfaced to the VSB demodulator for further
processing. In a typical application, the TDA8980 handles AGC,
eliminating the need for external components such as an op-amp loop
integrator.
It has an internal 2-D adaptive comb filter for NTSC, and a YUV
interface allows simple connection of additional picture enhancement
ICs such as a 3-D comb filter. For sound decoding, external
devices - a BTSC sounder decoder, for example - can be connected.
TDA8961 DTV DEMODULATOR/DECODER
General features
One-chip ATSC-compliant demodulator and concatenated
Trellis (Viterbi)/Reed-Solomon decoder with de-interleaver
and de-randomizer
Parallel (8-bit) or serial MPEG2 transport stream output
On-board I
2
C-bus interface
MPEG2 serial transport stream input
COMPLETE REFERENCE DESIGN FOR
HYBRID ATSC/NTSC RECEIVER FRONT-ENDS
This reference design demonstrates a complete solution for building hybrid ATSC/NTSC receiver front-ends for
HDTV sets, STBs and PC/multimedia applications, using just two highly integrated, second generation ICs.
11
MSD051
9
11
9
4
3
3
2
5
12
30
6
8
8
reset
reset
serial TS
output
diag
serial TS
input
9
TS in
I
2
C
EEPROM &
CONTROL
SAA7146
PCI connector
FPGA
Errror
+
5 V
+
12 V
VCC
TDA8961
(w/socket)
TDA8980
(w/socket)
TS
TS
+
diag
+
control
+
status
6
status
FIFO
12 MHz
AUDIO
MUX
stereo
audio in
4.5 MHz
TRAP
TUNER
tuner
AGC
12 MHz
FIFO
power
MPOC output
S/PDIF in
JTAG
IF AGC
CD in
CD out
I
2
C
I
2
C
I
2
S out
5 V
I
2
C
3 V
I
2
C
TS connector
diag
RGBS/YUVS
in
InRange_1
Tuner_Lock
FE_Lock
EQ_Lock
FSHNDSHK
FPGA_1
FPGA_2
FPGA_3
comp.
video
in S-video
in
reset
AUDIO
MIX
PCF9851
I
2
C ADC
TDA9851
BTSC
DECODER
TDA1315
VCC
I
2
S
out
I
2
S out
I
2
S in
L3
bus
parallel
output
8-VSB demodulator
On-chip digital tuner AGC control
Integrated digital Square-Root Raised-Cosine (half Nyquist)
filter with 11.5 % roll-off
Fully internal carrier recovery loop with programmable
loop filter
No need for external VCXO and DAC due to internal sample
rate converter
Fully internal symbol timing recovery with programmable
loop filters
Adaptive equalizer
Feed forward including a decision feedback equalizer (DFE)
Standard range: -2.3
s to +22.5
s (up to 80
s in conjunction
with external software)
Adaptation based on ATSC field sync (trained) and/or
8-VSB data (blind)
Additional complex equaliser to cope with highly dense
urban multipath
Patented adaptive NTSC co-channel filter technology,
with low/zero insertion loss
On-chip FEC
Trellis (Viterbi) decoder
Rate 2/3 (Rate 1/2 Ungerboeck-code-based)
(207, 187, T=10) Reed-Solomon decoder
Internal convolutional de-interleaving
ATSC standard-based de-randomizer
The TDA8961 is an ATSC-compliant device with forward error
correction, accepting 8-VSB modulated signals with the additional
ability to apply the VSB IC AGC control output directly to the
tuner. The combination of the TDA8980 and TDA8961 requires
only one 12 MHz crystal and when the TDA8980 is performing
NTSC decoding, the TDA8961 can be set in a feed-through mode,
enabling ITU656 data to appear at the MPEG2 transport stream
output for feeding to the graphics display IC. The demodulator can
also act as an MPEG2 Transport Stream switcher for an additional
serial stream.
After the TDA8961 has performed internal carrier recovery, Nyquist
filtering and symbol timing recovery, it carries out adaptive
equalization using the ATSC field sync (trained equalization)
and/or the 8-VSB data itself (blind equalization). This uses a decision
feedback equalizer (DFE) structure.
Once trellis decoding is complete, the stream
is de-interleaved with a convolutional
de-interleaver with on-chip memory.
The Reed-Solomon decoder is ATSC-
compliant, with a length of 207, and it can
correct up to 10 bytes. After the decoded
stream is de-randomized using a pseudo-
random bit sequence (PRBS), it outputs an
8-bit parallel or a serial MPEG2 transport
stream for subsequent de-multiplexing.
TD1536 tuner
Able to handle ATSC terrestrial signals as well
as NTSC and QAM, the TD1536 offers flat
frequency response, low oscillator phase noise
and excellent large signal handling
characteristics. Optimized for handling high
adjacent channel levels, through on-board
selectivity adjustment (SAW filter), the
TD1536 also provides internal automatic gain
control (AGC), minimizing design-in effort.
The TD1536's low output impedance makes
it capable of driving several SAW filters
(for example, second VSB and NTSC SAWs).
It is powered from a single 5V supply.
SAA7146A PCI bridge
For PC/multimedia applications, the reference
design includes the option to include the
SAA7146A PCI bridge. This device features
high performance 2D scaling, resulting in very
few artefacts even when pictures are reduced to
icon size, making it ideal for windowing and
high-end applications. It also has a hardware
vanity picture function and by performing
most of the video processing on-board, the
SAA7146A helps reduce load on the CPU,
maintaining high overall system performance.
In addition to the PCI-bus, it supports a
variety of interfaces including two ITU-R 656
ports, an Intel/Motorola 8/16-bit DEBI
(Digital Expansion Bus Interface), I
2
C and I
2
S
bus connectors, and a 4-bit general purpose
interface.
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1999
SCB62
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Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
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Printed in The Netherlands
Date of release:
March 1999
Document order number:
9397 750 05383
ATSC/NTSC digital TV front-end chipset
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